Abstract:

This work presents a compact-model-based delay analysis of a 0.5-µm gate-length GaN HEMT using small-signal parameters extracted from the MIT Virtual Source GaNFET-RF model. The delay framework separates the contributions of the intrinsic channel, extrinsic channel, and parasitic elements associated with access resistance and gate-to-drain Miller capacitance over a baseplate temperature range of 298–423 K. The results show that the total delay is dominated by the extrinsic channel, attributed to fringing-field coupling from the T-gate sidewalls, while parasitic delay contributes less than 13% of the total delay. This indicates that cutoff-frequency improvement is more likely to come from gate geometry and channel electrostatic optimization than from access-region resistance reduction alone. The cutoff frequency degrades at approximately 0.2%/K, primarily due to reduced transconductance and increased intrinsic gate-to-source capacitance at elevated temperature. These results provide a quantitative link between layout-dependent delay components, thermal degradation, and RF performance in
GaN HEMTs.